Field effect transistors are ubiquitous in modern electronics technology. This type of transistor has been primarily fabricated in single crystal silicon, i.e., in a single crystal wafer or in an epitaxial layer grown on a single crystal wafer. The high quality single crystal silicon has good properties for transistors in terms of, e.g., carrier transport and interface characteristics.
There are, however, applications where use of single crystal silicon is difficult or impossible. For example, field effect transistors are used in making active matrix liquid crystal displays. These transistors are fabricated on glass substrates. Additionally, static random access memories (SRAMs) can be fabricated in cells which have six transistors. Two transistors function as electrical loads and the cell size is reduced when the load transistors are fabricated above the other four transistors rather than in the same plane. In this case, the load transistors are fabricated in a material formed on a dielectric layer which separates the load transistors from the other four transistors. For use in these, as well as other, applications, thin film transistors (TFTs) have been developed. Such transistors are frequently fabricated using polysilicon, rather than single crystal silicon, as the channel material, i.e., the material in which the current flows.
TFTs for active loads in SRAM cells should satisfy several criteria, and the nature of the polysilicon determines how easily these criteria can be satisfied. One criterion of great interest is the ratio of the ON state current to the OFF state current. This ratio should be as large as is possible. The lower OFF state current indicates lower standby current, and the higher ON state current improves both performance and cell stability. Two primary factors influencing this ratio are the grain size of the silicon in the channel and the oxide/polysilicon interface, i.e., the interface between the oxide of the gate structure and the polysilicon of the channel. Larger grain size increases the carrier mobility as compared to smaller grain size and also increases the ON state current. Larger grains also result in less dopant diffusion from the source/drain regions into the channel. Such diffusion would result in a shorter effective channel and a greater OFF state current than would the longer channel. The larger grains also reduce the back channel leakage current and thereby reduce the OFF state current. The oxide/polysilicon interface is important because a poor quality interface may have many dangling bonds which result in charge trapping. More importantly, a poor interface enhances the surface scattering of carriers and thus decreases the effective carrier mobility. Similar considerations are applicable to the TFTs used for display purposes.
The quality of the polysilicon is thus important for device purposes and much attention has been directed toward forming polysilicon with the desired characteristics. For example, Mimura, IEEE Transactions on Electron Devices, 36, February 1989, pp. 351-359, describes the deposition of silicon by low-pressure chemical vapor deposition at temperatures between 500.degree. C. and 550.degree. C. followed by a 600.degree. C. anneal for 24 hours in nitrogen to recrystallize the silicon. The transition temperature between amorphous and poly structure is around 545.degree. C. To ensure a real amorphous structure, one has to deposit the Si at a temperature well below the transition temperature. To get the large grain polysilicon, one has to regrow the amorphous Si at a low regrowth rate, which means slightly higher than the transition temperature for a longer time to avoid secondary recrystallization. In the Japanese Journal of Applied Physics, 30, January 1991, pp. 184-187, Aoyama describes a two-step annealing process which reduces the leakage current. Amorphous silicon was deposited at 550.degree. C. and annealed for ten hours in a nitrogen atmosphere at 600.degree. C. to recrystallize the silicon. See also, IEEE Transactions on Electron Devices, ED-33, April 1986, pp. 477-481 for a discussion of thin film transistors.
Not only is the oxide/polysilicon interface important, the quality of the oxide is also important. Deposited oxides typically have poor dielectric quality and are sensitive to both the polysilicon structure and dopant concentration. Grown oxides are difficult to fabricate because of the limited thermal budget after the transistors' source-drain formation. Additionally, the surface morphology of the polysilicon, together with the limited thermal budget, makes conventional oxidation impractical.